Memory Timings Overclock Guide

Unfinished Guide to overclocking your RAM.

CAS Latency (tCL):

The CAS latency is the delay in clock cycles between sending a READ request and the moment the first piece of data is available on the outputs. The lower this number, the faster memory reads should be.

Write Recovery Time (tWR):

Write recovery time is the number of clock cycles taken between writing data and issuing the precharge command. tWR is necessary to guarantee that all data in the write buffer can be safely written to the memory core.













tRAS - Row Active Time:



tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.













tRC - Row Cycle Time:



The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.



tRC = tRAS + tRP













tRCD - Row Address to Column Address Delay:



tRCD is the number of clock cycles taken between the issuing of the active command and the read/write command. In this time the internal row signal settles enough for the charge sensor to amplify it.













tRP - Row Precharge Time:



tRP is the number of clock cycles taken between the issuing of the precharge command and the active command. In this time the sense amps charge and the bank is activated.













tRRD - Row Active to Row Active Delay:



The minimum time interval between successive ACTIVE commands to the different banks is defined by tRRD.













tCCD - Column Address to Column Address Delay













tRD - Active to Read Delay ?:













tWTR - Internal Write to Read Command Delay:



tWTR is the delay that has to be inserted after sending the last data from a write operation to the memory and issuing a read command.













tRDA - Read Delay Adjust













Memory timings are given as: CAS-tRCD-tRP